Active matrix substrate with TFT and capacitor, and LCD using the same

ABSTRACT

A thin-film transistor substrate, including a substrate with an insulating surface, gate electrodes, lower electrodes of capacitors made of the same material layer as the gate electrodes, a first insulating layer, a channel layer of high resistivity semiconductor having a concave part, and a pair of low resistivity source/drain electrodes. There is also a second insulating layer formed on the first insulating layer. A first connection hole penetrates the second insulating layer and exposes one of each of the pair of the source/drain electrodes. A second connection hole penetrates the second insulating layer and exposes a connection region of each of the upper layers of the upper electrode above the lower layer. A pixel electrode is formed on the second insulating layer and is connected to one of the source/drain electrodes and the upper layer of the upper electrode of the capacitor via the first and second connection holes.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on Japanese Patent Application 2001-387961,filed on Dec. 20, 2001, the entire contents of which are incorporatedherein by reference.

BACKGROUND OF THE INVENTION

A) Field of the Invention

This invention relates to a thin film transistor (TFT) substrate and aliquid crystal display and especially to those having additional orsubsidiary storage capacitors.

B) Description of the Related Art

Recently, a liquid crystal display is widely used for an informationdevice, etc., and lower cost and higher resolution are sought. Most ofthin film transistor substrates have additional or subsidiary storagecapacitors for storing information for pixel electrodes at respectivepixels. The additional storage capacitor is generally formed with anopaque body, and therefore causes a reduction in an effective pixelarea. Miniaturization of the additional storage capacitor that occupiesa comparatively large region is demanded. Also, in a manufacturingprocess of the additional storage capacitor, interlayer short-circuitetc. causes defections. Decreasing the defections is expected.

FIGS. 5A to 5D show examples of configurations of thin film transistorsubstrates according to the prior art.

FIG. 5A is a plan view showing a thin film transistor substrate by theconventional technology. FIG. 5B is a cross sectional view showing apart of a thin film transistor along the line VB—VB in FIG. 5A, and FIG.5C is a cross sectional view showing an additional storage capacitorpart along the line VC—VC in FIG. 5A.

A gate bus line 2 t and an additional storage capacitor bus line 2 c areformed by patterning a metallic layer on a substrate 1 having aninsulating surface such as a glass substrate or the like. The bus lines2 t and 2 c are electrically isolated from each other. An insulatinglayer 3 such as a silicon nitride or the like is formed on the entiresurface of the substrate 1 so as to cover the bus lines 2 t and 2 c. Theinsulating layer 3 forms a gate insulating film 3 t in the thin filmtransistor region and a dielectric film of a capacitor 3 c in theadditional storage capacitor region.

A high resistivity amorphous silicon layer that can form a thin filmtransistor channel (11 t, 11 c) is deposited on an insulating layer 3,and thereon a silicon nitride layer having a function of an etchingstopper is deposited. The silicon nitride layer is patterned to remainas a channel protection layer 12 t only in the thin film transistorchannel region. An n⁺-type amorphous silicon layer that is highly dopedwith n-type impurity is deposited on the high resistivity amorphoussilicon layer so as to cover the channel protection layer 12 t. Theamorphous silicon layer and the silicon nitride layer are deposited by,for example, chemical vapor deposition (CVD).

A Ti layer 4 a, an Al layer 4 b and a Ti layer 4 c are laminated on anamorphous silicon layer, for example, by sputtering. A resist pattern isformed on the Ti layer 4 c, and the Ti layer 4 c, the Al layer 4 b, theTi layer 4 a, the n⁺ type amorphous silicon layer and the highresistivity amorphous silicon layer are patterned into, respectively. 13t/13 c and 11 t/11 c. The channel protection layer 12 t is formed on thechannel region; therefore, the etching on the channel region is stoppedat the channel protection layer 12 t, and the high resistivity amorphoussilicon layer underneath is not etched.

As described above, source/drain electrodes and an upper electrode ofthe capacitor are formed in the thin film transistor region and theadditional storage capacitor region.

Covering the Ti layer 4 c, an insulating protection layer 14, forexample, of silicon nitride, is deposited on an insulating layer 3 byCVD or the like. Contact apertures 8 t and 8 c are formed on a sourceregion of the thin film transistor and an upper electrode of aconnecting region of the additional storage capacitor. In this etchingprocess, for example, if a pinhole exists on the Ti layer 4 c, the Allayer 4 b and the Ti layer 4 a, the etching reaches the layerunderneath.

When a pinhole exists in a metallic lamination at the bottom of aconnection hole 8 c in FIG. 5C, the etching reaches the amorphoussilicon layers 13 c, 11 c, and the lower insulating layer 3 c, and mayreach the lower electrode 2 c.

Then, an indium-tin oxide (ITO) layer 5 is deposited on the insulatingprotection layer 14 covering the connection hole, and patterned to forma pixel electrode. If the lower electrode 2 c is exposed by a pinhole, apixel electrode 5 short-circuits the lower and the upper electrodes, anda capacitor loses its function.

FIG. 5D shows an example of a structure having a contact of the upperelectrode to the pixel electrode outside the lower electrode to preventthe short circuit. Because the contact of the upper electrode is formedoutside the lower electrode, the short circuit can be prevented even ifa pinhole exists. However, the lower and the upper electrodes are bothopaque layers so that an effective area of the pixel electrode decreasesin such degree that the upper electrode extends outside the lowerelectrode.

In the thin film transistor substrate having an additional storagecapacitor, preventing the short circuit between the electrodes of theadditional storage capacitor and obtaining a valid pixel area as largeas possible were difficult.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a thin filmtransistor substrate and a liquid crystal display that can prevent ashort circuit between electrodes of an additional storage capacitor andobtain a larger valid pixel region at the same time.

It is another object of the present invention to provide a thin filmtransistor substrate and a liquid crystal display having a novelstructure.

According to one aspect of the present invention, there is provided athin-film transistor substrate comprising a substrate having aninsulating surface, gate electrodes made of a conductive material layerformed on said substrate, lower electrodes of capacitors made of a samematerial layer as said gate electrode and formed on said substrate, afirst insulating layer formed on said substrate and covering said gateelectrodes and said lower electrodes of the capacitors, a channel layerof high resistivity semiconductor formed on said first insulating layerover each said gate electrode, a lower layer of each upper electrode ofthe capacitors made of a same material layer as said channel layer andformed on said first insulating layer above said lower electrodes of thecapacitor, a channel protection layer formed on an intermediate part ofeach said channel layer, a capacitor protection layer made of a samematerial layer as said channel protection layer and formed on aconnection region of each said lower layer of the upper electrode of thecapacitor, a pair of n⁺-type source/drain electrodes formed on each saidchannel layer, the source/drain electrodes being separated from eachother on said channel protection layer, an upper layer of the upperelectrode of the capacitor made of a same material layer as saidsource/drain electrodes, formed on each said lower layer of the upperelectrode of the capacitor, and covering said capacitor protectionlayer, a second insulating layer formed on said first insulating layerand covering said source/drain electrodes and said upper layers of theupper electrode of the capacitor, a first connection hole penetratingsaid second insulating layer and exposing each one of said pair of thesource/drain electrodes, a second connection hole penetrating saidsecond insulating layer and exposing a connection region of each of saidupper layers of the upper electrode of the capacitor, and a pixelelectrode formed on said second insulating layer and connected to eachone of said source/drain electrodes and said upper layer of the upperelectrode of the capacitor via said first connection hole and saidsecond connection hole.

According to another aspect of the present invention, there is provideda thin-film transistor substrate comprising a substrate having aninsulating surface, gate electrodes made of a conductive material layerformed on said substrate, lower electrodes of capacitors made of a samematerial layer as said gate electrode and formed on said substrate, afirst insulating layer formed on said substrate and covering said gateelectrodes and said lower electrodes of the capacitors, a channel layerof high resistivity semiconductor having a concave part on a surfaceabove each of said gate electrodes and formed on said first insulatinglayer over each of said gate electrodes, a lower layer of an upperelectrode of the capacitor having no concave part on a surface, made ofa same material layer as said channel layer, and formed on said firstinsulating layer above each of said lower electrodes of the capacitors,a pair of low resistivity source/drain electrodes formed on regions onboth sides of each of said concave parts of said channel layers, anupper layer of the upper electrode of the capacitor made of a samematerial layer as said source/drain electrodes and formed on said lowerlayer of each of the upper electrodes of the capacitors, a secondinsulating layer formed on said first insulating layer and covering saidsource/drain electrodes and said upper layer of the upper electrode ofthe capacitor, a first connection hole penetrating said secondinsulating layer and exposing one of each of said pair of thesource/drain electrodes, a second connection hole penetrating saidsecond insulating layer and exposing a connection region of each of saidupper layers of the upper electrode of the capacitor; and a pixelelectrode formed on said second insulating layer and connected to saidone of the source/drain electrodes and said upper layer of the upperelectrode of the capacitor via said first connection hole and saidsecond connection hole.

According to further aspect of the present invention, there is provideda liquid crystal display comprising the above-described thin-filmtransistor substrate, a color filter substrate wherein a color filterand a transparent common electrode are formed on a transparentsubstrate, and a liquid crystal layer held between said thin-filmtransistor substrate and said color filter substrate.

The short-circuiting between the electrodes of the additional storagecapacitor can be prevented while obtaining a large valid area of thepixel electrode. A new structure of the thin film transistor and theliquid crystal display device are given.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A–1D are a plan view and cross-sectional views showing a thinfilm transistor substrate according to an embodiment of this invention.

FIGS. 2A–2C are an equivalent circuit diagram of the thin filmtransistor substrate and cross-sectional views of a modified example ofthe embodiment shown in FIGS. 1A–1D.

FIG. 3 is a cross-sectional view showing the liquid crystal display.

FIG. 4 is a plane view showing a structure of a thin film transistorsubstrate according to another embodiment of this invention.

FIGS. 5A–5D are a plan view and cross sectional views for explaining astructure of a thin film transistor substrate according to the priorart.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A–1D are a plan view and cross-sectional views showing astructure of a thin film transistor (TFT) substrate according to anembodiment of this invention. FIG. 1B is a cross sectional view showingthe thin film transistor region along a line IB—IB in FIG. 1A, and FIG.1C is a cross sectional view showing an additional or auxiliary storagecapacitor region along a line IC—IC in FIG. 1A.

A gate bus line 2 t and an additional storage capacitor bus line 2 c areformed on the glass substrate 1 by depositing an electrode layer, forexample by sputtering a layer, and patterning the layer byphotolithography. A transparent substrate is used for a transparentliquid crystal display. An opaque substrate other than a transparentsubstrate can be used for a reflective liquid crystal display, althoughthe surface should be insulated. A substrate having an insulatingsurface, for example a silicon substrate with an oxide film, a metalplate having an insulating layer on the surface, etc. can be used.

As shown in FIG. 1D, this electrode layer is preferably formed bylaminating, for example, an Al layer 2-1 with a thickness of about 10 nmfor the lower layer and a Ti layer 2-2 with a thickness of about 50 nmfor the upper layer.

After patterning the electrode layer, an insulating layer 3 made of, forexample, a Si₃N₄ 3 layer with a thickness of 400 nm is deposited by, forexample, CVD. This insulating film 3 forms a gate insulating layer 3 tin the thin film transistor region and a dielectric film of a capacitor3 c in the additional storage capacitor.

For example, a high resistivity amorphous silicon layer with a thicknessof 30 nm that can form a thin film transistor channel 11 t, 11 c isdeposited on the insulating layer 3 by, for example, CVD. On the highresistivity amorphous silicon layer, for example, a Si₃N₄3 layer with athickness of about 150 nm as an etching stopper layer is deposited byCVD. The Si₃N₄3 layer is patterned by photolithography and etching toremain a channel protection layer 12 t in the thin film transistorregion and to remain a capacitor protection layer 12 c in the additionalstorage capacitor region.

On the high resistivity amorphous silicon layer, for example, an n⁺ type(low resistivity) amorphous silicon layer with a thickness of 30 nm isdeposited by CVD while covering those insulating layers 12 t and 12 c.Thereon, for example, a Ti layer 4 a with a thickness of about 20 nm, Allayer 4 b with a thickness of about 75 nm and Ti layer 4 c with athickness of about 40 nm are deposited sequentially by sputtering.

Then a resist pattern is formed on the Ti layer 4c, for example, Tilayer 4 c, Al layer 4 b and Ti layer 4 a are etched by reactive ionetching (RIE) using C1-cintaining etching gas, further an n⁺ typeamorphous silicon layer and a high resistivity amorphous silicon layerare etched into, respectively. 13 t/13 c and 11 t/11 c.

The channel protection layer 12 t works as an etching stopper andprotects a high resistivity silicon layer 11 t underneath. At the bothsides of channel protection layers 12 t, an n⁺ type silicon layer 13 tcontacts the high resistivity silicon layer 11 t. As described above, apair of source/drain electrodes S and D is formed in separated regionson the channel layer 11 t.

Also, in the additional storage capacitor region, a capacitor protectionlayer 12 c is remained only in a limited region, and around that region,an n⁺ type silicon layer 13 c contacts with the high resistivity siliconlayer 11 c underneath. The high resistivity silicon layer 11 c, the n⁺type silicon layer 13 c, and the metal electrodes 4 a, 4 b and 4 c forman upper electrode of the capacitor.

Then while covering the source/drain electrodes S, D and the upperelectrodes, an upper protection layer 14 of the Si₃N₄ layer, forexample, with a thickness of about 300 nm is deposited by CVD. The upperprotection layer 14 may be formed of an organic insulating layer, etc.,other than the Si₃N₄ layer. A resist pattern is formed on the Si₃N₄layer 14, and etching is performed to open a connection hole on thesource electrode S and the upper electrode. At this time, the drainelectrode D is covered with the resist pattern.

This etching is performed by RIE using F-containing dry etchant, forexample, CF₄, CHF₃, SF₆ or the like. Even if a pinhole exists at theupper electrode 4 c of the capacitor, the surface of the lower electrode2 c is not exposed unless the high resistivity silicon layer 11 c andthe Si₃N₄ layer 3 c are etched. Therefore, an opening 8 c is formedwhile preventing a short circuit between the lower electrode and theupper electrode.

Further, in the source electrode S of the thin film transistor, anopening 8 t is also formed. In the source electrode S, even if a pinholeexists, only a part of the source electrode S is etched, therefore thefunction is not affected very much.

After forming the opening at the Si₃N₄ layer 14, the ITO layer isdeposited thereon, and patterned by etching to form a transparent pixelelectrode 5. The upper electrode of the capacitor is connected to thesource electrode S via the transparent pixel electrode 5, and when adrive voltage is given to the pixel electrode via the drain electrode Dand the source electrode S, the voltage can be stored in the capacitor.

Although description has been made on the case wherein the thin filmtransistor is formed by using the amorphous silicon layer, the amorphoussilicon layer may be converted to a polycrystalline silicon layer byannealing with a XeCI laser after depositing the amorphous siliconlayer. The polycrystalline silicon layer can improve the performance ofthe thin film transistor.

FIG. 2A shows an equivalent circuit diagram of a circuit formed on thethin film transistor substrate. A plurality of drain bus lines DB areformed in vertical direction. A plurality of gate bus lines GB andadditional storage capacitor bus lines CSB are formed in horizontaldirection.

A thin film transistor TR is connected to each cross point of the drainbus line DB and the gate bus line GB. A drain electrode D of the thinfilm transistor TR is connected to the drain bus line DB, an insulatedgate electrode is connected to the gate bus line GB, and a sourceelectrode S is connected with a transparent pixel electrode PX.

A capacitor C is connected between each of the transparent pixelelectrodes PX and an additional storage capacitor bus line CSB. Theadditional storage capacitor bus line CSB is maintained at a constantvoltage, for example, a ground voltage, and the capacitor C stores animage signal voltage supplied via the drain electrode D from the drainbus line DB. Although the figure shows the structure of two rows and twocolumns, more rows and columns are formed in actual thin film transistorsubstrates.

Although description has been made on the structure wherein an etchingstopper is formed on the channel layer, the etching stopper can beomitted by making the channel layer thick.

FIGS. 2B and 2C show structures using a channel etch-type thin filmtransistor. Similar reference symbols are given to similar elements asin FIG. 1 and detailed explanations will be simplified.

After an insulating layer 3 forming a gate insulating layer 3 t and adielectric layer of a capacitor 3 c is deposited, a high resistivityamorphous silicon layer 11 that can form a channel is deposited, andthereon an n⁺-type amorphous silicon layer 13 highly doped with n-typeimpurity is deposited. Then, a resist pattern is formed on the n⁺-typeamorphous silicon layer 13, and the n⁺-type amorphous silicon layer 13and the n-type amorphous silicon layer 11 are patterned by etching toremain the silicon layers 13 t, 11 t, 13 c and 11 c only in the thinfilm transistor region and the additional storage capacitor region.

Then, a metal electrode 4 is deposited, and source/drain electrodes 4 tand an upper metal electrode of the capacitor 4 c are patterned byetching. In this etching, although the n⁺-type amorphous silicon layer13 t is etched, part of the thickness of the high resistivity amorphoussilicon layer 11 t underneath remains by controlling the etching amountafter etching the metal electrode layer. In the additional storagecapacitor region, the amorphous silicon layers 13 c and 11 c arecompletely covered by the metal electrode 4 c.

Thereafter, similar to the above-described embodiment, a Si₃N₄ layer 14is deposited, and connection holes 8 t and 8 c penetrating the Si₃N₄layer 14 are formed by etching. After opening the connection holes 8 tand 8 c, a transparent pixel electrode 5 is deposited and patterned.

When the connection holes 8 t and 8 c are etched on the Si₃N₄ layer,even if a pinhole exists in the metal electrode layer, etching is doneto the silicon layers 13 c and 11 c underneath at first, then to theSi₃N₄ layer 3 c. Therefore the etching can be stopped before exposingthe lower electrode 2 c, and the short circuit between the upperelectrode and the lower electrode can be prevented.

FIG. 3 shows a state when a liquid crystal display is formed by usingthe above-described thin film transistor substrate and a well-knowncolor filter substrate. Pixel electrodes PX are formed on the surface ofthe thin film transistor substrate TRS.

On the surface of the opposing color filter substrate CFS, for examplered, green and blue color filters CF are formed, and a transparentcommon electrode CT made of ITO and being common to a whole displayregion is formed on the color filters CF. Further, insulatingprotrusions VA are formed in limited regions. In the part where theprotrusion VA exists, a distribution of electric force lines isadjusted.

In the state when a voltage is not applied between the electrodes,liquid crystal molecules of a liquid crystal layer are orientatedvertical to the surface of the substrate. When a voltage is appliedbetween the electrodes, the liquid crystal molecules in the liquidcrystal layer LC are modulated the orientation to be arranged verticalto the electric force lines. On the protrusions VA, the orientation ofthe liquid crystal molecules is inclined when the voltage is notapplied. Therefore direction of collapse of the liquid crystal moleculesis controlled when a voltage is applied. Therefore, a multi-verticalalignment (MVA) liquid crystal display which has plural areas ofdifferent orientation is formed.

The additional storage capacitor is not limited to the case where theadditional storage capacitor bus line is formed separately from the gatebus line. Also, the additional storage capacitor can be formed by usingthe gate bus line.

FIG. 4 shows an example of the structure that forms the additionalstorage capacitor on the gate bus line. A gate bus line 2 t contains aregion for forming a thin film transistor, and also a region for formingan additional storage capacitor. After a gate insulating layer is formedon the gate bus line, a high resistivity amorphous silicon layer formingthe channel and a Si₃N₄ layer as an etching stopper are deposited. TheSi₃N₄ layer is selectively etched to remain a channel protecting film 12t in the thin film transistor region on the gate bus line and to remainthe capacitor protecting film 12 c in the additional storage capacitorregion.

By depositing an n⁺-type amorphous silicon layer that forms thesource/drain electrodes and an upper electrode and a metal electrodelayer and by patterning them, source/drain electrodes 4 t are formed inthe thin film transistor region, and an upper electrode 4 c is alsoformed in the additional storage capacitor region. Then, the thin filmtransistor substrate is formed by the steps similar to theabove-described embodiment.

The upper electrode 4 c is connected to the transparent pixel electrode5 of the upper side in the figure via the connection hole 8 c. By thisstructure, the voltage applied to the upper electrode of the additionalstorage capacitor is the voltage at the next pixel, and the gate busline 2 t is maintained at the constant voltage at that time. Therefore,an electric charge is effectively stored in the additional storagecapacitor.

Although description has been made on the case where the gate bus lineand the lower electrode of the additional storage capacitor are formedof Al/Ti lamination, the gate bus line may be formed of otherconductive. For example, a Cr single layer and an Al/Mo lamination canbe used.

Although description has been made on the case where the gate insulatingfilm, the etching stopper layer and the upper insulating protecting filmare formed of silicon nitride layers, other insulating layers can beused. For example, silicon oxide layers and silicon oxide nitride layerscan be used. Also the combination of a plural types of insulating layerscan be used.

Although description has been made on the case when the metal electrodesof the source/drain electrodes are formed of a Ti/Al/Ti lamination,other conductive layers may be used. For example, a Cr single layer anda Mo/Al/Mo lamination may be used.

The present invention has been described in connection with thepreferred embodiments. The invention is not limited only to the aboveembodiments. It will be apparent for those skilled in the art thatvarious modifications, improvements, combinations, and the like can bemade.

1. A thin-film transistor substrate, comprising: a substrate having aninsulating surface; gate electrodes made of a conductive material layerformed on said substrate; lower electrodes of capacitors made of a samematerial layer as said gate electrodes and formed on said substrate; afirst insulating layer formed on said substrate and covering said gateelectrodes and said lower electrodes of the capacitors; a channel layerof high resistivity semiconductor having a concave part of a reducedthickness on a surface above each of said gate electrodes and formed onsaid first insulating layer over each of said gate electrodes; a lowerlayer of an upper electrode of the capacitor having no concave part on asurface, made of a same material layer as said channel layer, and formedon said first insulating layer above each of said lower electrodes ofthe capacitors, with said lower layer of the upper electrode beingpatterned to be located in a connection region; a pair of lowresistivity source/drain electrodes formed on regions on both sides ofeach of said concave parts of said channel layers; an upper layer of theupper electrode of the capacitor made of a same material layer as saidsource/drain electrodes and formed to envelope said lower layer of eachof the upper electrodes of the capacitors; a second insulating layerformed on said first insulating layer and covering said source/drainelectrodes and said upper layer of the upper electrode of the capacitor;a first connection hole penetrating said second insulating layer andexposing one of each of said pair of the source/drain electrodes; asecond connection hole penetrating said second insulating layer andexposing a connection region of each of said upper layers of the upperelectrode of the capacitor above said lower layer; and a pixel electrodeformed on said second insulating layer and connected to said one of thesource/drain electrodes and said upper layer of the upper electrode ofthe capacitor via said first connection hole and said second connectionhole.
 2. The thin-film transistor substrate according to claim 1,wherein each of said gate electrodes and each of said lower electrodesof the capacitors are made of parts of an electrically isolated bus lineformed on said substrate.
 3. The thin-film transistor substrateaccording to claim 1, wherein said gate electrode and said lowerelectrode of the capacitor are made of different parts of a gate busline formed on said substrate.
 4. The thin-film transistor substrateaccording to claim 1, wherein said lower layer of the upper electrode ofthe capacitor is made of a high resistivity amorphous silicon layer, andsaid source/drain electrodes and said upper layer of the upper electrodeof the capacitor comprise a doped amorphous silicon layer formed on saidhigh resistivity amorphous silicon layer.
 5. The thin-film transistorsubstrate according to claim 1, wherein said lower layer of the upperelectrode of the capacitor is located within a region above anassociated one of said lower electrodes of the capacitor.
 6. Thethin-film transistor substrate according to claim 5, wherein said upperlayer of the upper electrode covers the lower layer of the upperelectrode.
 7. The thin-film transistor substrate according to claim 5,wherein said second connection hole is located within a region abovesaid lower layer of the upper electrode.
 8. The thin film substrateaccording to claim 1, wherein said channel layer of high resistivitysemiconductor is of a substantially uniform thickness except for an areaof said reduced thickness.